Yifan Qin

Yifan Qin

PhD candidate in department of computer science engineering

About

I am a fourth-year Ph.D. candidate in Computer Science and Engineering at the University of Notre Dame. I am working at the intersection of machine learning and computer architecture, focusing on inference-efficient LLMs and hardware-aware optimization under realistic system and device constraints. Research spans algorithm–system co–design, robustness/uncertainty-aware training, and runtime–oriented evaluation.

You can find my CV here.

I am actively seeking industry internships and full-time opportunities.
Contact: yqin3 [at] nd [dot] edu

Research Experiences

  • Research Assistant
    University of Notre Dame, Notre Dame, IN | Aug 2022 - present
    • Developed hardware aware training and inference strategies for deep learning models on resource and device constrained accelerators (e.g., compute-in-memory), introducing a negative feedback based optimization framework (NeFT) to improve robustness and accuracy–efficiency tradeoffs under device variation and runtime constraints.
    • Proposed a lightweight parameter sharing mechanism (TSB) for parameter efficient fine tuning and inference under memory and runtime constraints, reducing inference overhead while preserving model performance in hardware constrained settings.
    • Developed the software and uncertainty aware inference algorithms for an end-to-end arrhythmia detection engine, including uncertainty analysis to characterize prediction reliability under noise and device variation, and supported an ISSCC 2025 silicon prototype demo achieving 1.75 μJ per inference under practical latency and energy constraints.
    • Contributed to a tail robustness training approach using right censored noise to improve realistic worst case performance under hardware noise and variation, and the resulting paper received the ICCAD Best Paper Award.
  • Research Internship
    AI Chip Center for Emerging Smart Systems (ACCESS), Hong Kong | May 2024 - July 2024
    • Co-designed an end to end arrhythmia detection system with a CNN accelerator under strict latency and energy constraints, translating model requirements into deployment ready algorithm and system decisions.
    • Optimized the model for hardware constraints, including quantization and pruning, reducing inference cost while preserving detection accuracy in an accelerator based pipeline.
    • Implemented and integrated the software stack for real time inference and monitoring, supporting an ASP-DAC system demo on hardware prototypes at 10.60 μW and 150 GOPS under practical runtime constraints.
  • Research Assistant
    Huazhong University of Science and Technology, Wuhan, China | Aug 2018 - Jun 2022
    • Studied hardware aware low precision learning and inference for CNN accelerators, improving robustness and accuracy–efficiency tradeoffs under non ideal device behavior in memristive and crossbar based computing.
    • Published two papers on robust and energy efficient accelerator oriented inference, including a journal back cover feature.

Selected Publications

Journal

  1. Yifan Qin, Zheyu Yan, Dailin Gan, Jun Xia, Zixuan Pan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. “NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators”. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’25).

  2. Yifan Qin, Han Bao, Feng Wang, Jia Chen, Yi Li, and Xiangshui Miao. “Recent progress on memristive convolutional neural networks for edge intelligence”. In: Advanced Intelligent Systems (AIS’20) (Journal Back Cover).

  3. Yifan Qin, Rui Kuang, Xiaodi Huang, Yi Li, Jia Chen, and Xiangshui Miao. “Design of high robustness BNN inference accelerator based on binary memristors”. In: IEEE Transactions on Electron Devices (TED’20).

  4. Han Bao, Yifan Qin, Jia Chen, Ling Yang, Jiancong Li, Houji Zhou, Yi Li, and Xiangshui Miao. “Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks”. In: Frontiers in Electronics (FE’22).

Conference

  1. Yifan Qin, Zheyu Yan, Zixuan Pan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. “TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators”. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD’24, acceptance rate 24%).

  2. Yifan Qin, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi, “Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators”. In: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’24).

  3. Likai Pei*, Yifan Qin*, Zephan M. Enciso, Boyang Cheng, Jianbo Liu, Steven Davis, Zhenge Jia, Michael Niemier, Yiyu Shi, X. Sharon Hu and Ningyuan Cao. “Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks”. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD’24, acceptance rate 24%). (*Equal contribution)(2024 William J. McCalla Best Paper Award Candidate, 10 out of 802 submissions)

  4. Yifan Qin, Zhenge Jia, Zheyu Yan, Jay Mok, Manto Yung, Yu Liu, Xuejiao Liu, Wujie Wen, Luhong Liang, Kwang-Ting Tim Cheng, X. Sharon Hu and Yiyu Shi, “A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection,” in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC’25).

  5. Zheyu Yan, Yifan Qin, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. “Improving realistic worst-case performance of NVCiM DNN accelerators through training with right-censored Gaussian noise”. In: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD’23, acceptance rate 22.9%). (2023 William J. McCalla Best Paper Award, 2 out of 750 submissions)

  6. Yifan Qin, Jiahao Zheng, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi, “When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Accelerators”. In: International VLSI Symposium on Technology, Systems and Applications (VLSI TSA’26).

  7. Jianbo Liu, Zephan Enciso, Boyang Cheng, Likai Pei, Steven Davis, Yifan Qin, Zhenge Jia, Xiaobo Sharon Hu, Yiyu Shi and Ningyuan Cao, “A 65nm Uncertainty-quantifiable Ventricular Arrhythmia Detection Engine with 1.75μJ per Inference,” in Proc. of IEEE International Solid- State Circuits Conference (ISSCC’25).

  8. Zheyu Yan, Yifan Qin, Xiaobo Sharon Hu, and Yiyu Shi. “On the viability of using LLMs for SW/HW co-design: An example in designing CiM DNN accelerators”. In: 2023 IEEE 36th International System-on-Chip Conference (SOCC’23).

  9. Zixuan Pan, Kaiyuan Tang, Jun Xia, Yifan Qin, Lin Gu, Chaoli Wang, Jianxu Chen, Yiyu Shi, “SGI: Structured 2D Gaussians for Efficient and Compact Large Image Representation”. In: 2026 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR’26).

Patent

  1. A hardware neural network batch normalization system
    {CN202011251999.9 · Issued May 20, 2022}
  2. A matrix-vector multiplication circuit and calculation method
    {CN201910792384.8 · Issued Oct 8, 2021}

ML Demo

  • 06/2024 Real-Time Ventricular Arrhythmia Detection: Efficient ML Inference System — ACCESS Center, Hong Kong [Video]

    Demo: end-to-end inference system on a silicon prototype achieving 10.60 μW and 150 GOPS under strict latency/energy budgets.

    Co-design highlights

    • Model → Hardware: quantization + structured pruning to meet power/throughput targets while preserving detection accuracy
    • System → Runtime: implemented and integrated the real-time inference pipeline on hardware prototypes, including data I/O and runtime control
    • Monitoring & UI: built a live monitoring dashboard to visualize streaming signals, predictions, and system status for end-to-end observability during the demo
    • Validation: end-to-end evaluation under practical runtime constraints for safety-critical deployment

    Demo snapshots: real-time inference pipeline, hardware-integrated deployment, and monitoring interface.

    demo chip ui

  • 02/2025 Uncertainty-Aware ML Inference for Real-Time Ventricular Arrhythmia Detection — ISSCC, San Francisco [Video]

    Demo: uncertainty-aware inference system on a silicon prototype achieving 1.75 μJ per inference, targeting reliable arrhythmia detection under strict energy and reliability constraints.

    Co-design highlights

    • Algorithms: led Bayesian inference and uncertainty modeling for risk-aware decision-making
    • Robustness: evaluated reliability under OOD inputs and hardware non-idealities/variation
    • System integration: contributed to end-to-end integration for real-time inference on hardware prototypes
    • Monitoring: supported real-time monitoring for streaming signals, predictions, and uncertainty during the demo

    Demo snapshots: real-time uncertainty-aware inference pipeline and system validation.

Honors & Awards

  • William J. McCalla Best Paper Award, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023

  • William J. McCalla Best Paper Award Candidate, IEEE/ACM ICCAD, 2024

  • Young Fellow, Design Automation Conference (DAC), 2023–2025

  • Outstanding Graduate, Huazhong University of Science and Technology (HUST)

  • National Second Prize, China Undergraduate Mathematical Contest in Modeling (CUMCM; Ministry of Education, China) (2015)

Selected Review Experience

  • Scientific Reports
  • Great Lakes Symposium on VLSI Conference (GLSVLSI’25)
  • the International Conference on Acoustics, Speech, and Signal Processing (ICASSP’25)

Talks

  • Department of Computer Science, Shandong University (SDU), Aug 2024
    Efficient and Robust Machine Learning under System and Noise Constraints

  • Department of Electrical Engineering, Zhejiang University (ZJU), Aug 2024
    Uncertainty-aware ML Inference for Real-World Deployment

  • University of Michigan – Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Aug 2024
    Robust and Efficient ML Systems: From Training to Deployment

  • Department of Electrical Engineering, Southern University of Science and Technology (SUSTech), Jul 2024
    Efficient ML Inference for Resource-Constrained Systems

  • AI Chip Center for Emerging Smart Systems (ACCESS), Hong Kong University of Science and Technology, Jun 2024
    End-to-End Efficient ML Systems under Practical Constraints

talk

About Me (Optional)

  • President
    Table Tennis Association of Huazhong University of Science and Technology
    Wuhan | Aug 2014 - Aug 2015
    Manage and organize school sports competitions and liaise with the Sports Academy secretary and finance department for project reporting and financial reimbursement

  • Member
    Team of Undergraduate Mathematical Modeling of Huazhong University of Science and Technology
    Wuhan | Mar 2014 - Sep 2014
    National Second Prize in the China Contemporary Undergraduate Mathematical Contest in Modeling

  • Athlete
    College table tennis team in Huazhong University of Science and Technology
    Wuhan | May 2014 - Sep 2016
    It is an honor to serve as one of the college team with many professional players, many of whom have become my good friends.

  • Museum Docent
    Wuhan Museum | Aug 2015 - Aug 2016

    • The museum’s opening introduction. (PIC: Wuhan museum, main hall painting)

    museum painting

    • The Ming dynasty (1368 AD to 1644 AD) and Qing dynasty (1644 AD to 1911 AD) artifacts historical introduction. (PIC: Artifact example)

    artifact

Outside of research, I have a long-standing interest in art and creative expression.
One of my paintings was included in a provincial-level art textbook published by the People’s Education Press in China.

I enjoy drawing and writing, activities that foster imagination and long-term creative thinking.
I also stay active through sports, including table tennis and soccer, and regularly work out at the gym.

“风筝不断线” — Guanzhong Wu