Yifan Qin

Yifan Qin

PhD student in department of computer science engineering

About

I am a 3nd-year PhD student from Department of Computer Science and Engineering, University of Notre Dame. My research interest includes efficient and robust AI, software/hardware codesign, AI accelerator, and efficient LLM. Now I am very fortunate to work with Prof. Yiyu Shi and Prof. X. Sharon Hu, University of Notre Dame. Before my PhD study, I received BS and MS degree from Huazhong University of Science and Technology.

You can find my CV here.

Feel free to contact me if you have any idea or project to share, email: yqin3 [at] nd [dot] edu.

News

  • 🎉️Our paper is accepted by ISSCC 2025 ! A 65nm Uncertainty-quantifiable Ventricular Arrhythmia Detection Engine with 1.75μJ per Inference
  • 🎉️Our paper is selected as the Best Paper Candidate in ICCAD 2024 ! Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks
  • 🎉️Our paper is accepted by ASP-DAC 2025 ! A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection
  • 🎉️Our paper is accepted by ICCAD 2024 ! TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators
  • 🎉️Our paper is accepted by ICCAD 2024 ! Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks
  • 🎉️I give a talk on ACCESS summer school !
  • 🎉️Our poster is on ACCESS Techonlogy Symposium !
  • 🎉️Our paper is selected as the Best Paper in ICCAD 2023 ! Improving realistic worst-case performance of NVCiM DNN accelerators through training with right-censored gaussian noise
  • 🎉️Our paper is on arxiv ! Negative Feedback Training: A Novel Concept to Improve Robustness of NVCIM DNN Accelerators
  • 🎉️Our paper is accepted by Advanced Intelligent Systems and selected as Back Cover ! Recent progress on memristive convolutional neural networks for edge intelligence
  • 🎉️Our paper is accepted by IEEE Transactions on Electron Devices ! Design of high robustness BNN inference accelerator based on binary memristors

Talks

  • A talk is given in Computer science department, Shandong University (SDU), Aug 2024.
  • A talk is given in Electrical engineering department, Zhejiang University (ZJU), Aug 2024.
  • A talk is given in University of Michigan – Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University (SJTU), Aug 2024.
  • A talk is given in Electrical engineering department, Southern University of Science and Technology (SUSTech), July 2024.
  • A talk is given in AI Chip Center for Emerging Smart Systems (ACCESS), Hong Kong University of Science and Technology (HKUST), June 2024.

talk

Experiences

  • Intern - AI Chip Center for Emerging Smart Systems(ACCESS), Hong Kong University of Science and Technology (HKUST), May 2024 - July 2024.
  • Research Assistant - Huazhong University of Science and Technology (HUST), August 2018 - June 2022.

Publications

Journal

  1. Han Bao, Yifan Qin, Jia Chen, Ling Yang, Jiancong Li, Houji Zhou, Yi Li, and Xiangshui Miao. “Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks”. In:Frontiers in Electronics 3 (2022), p. 954661.
  2. Yifan Qin, Han Bao, Feng Wang, Jia Chen, Yi Li, and Xiangshui Miao. “Recent progress on memristive convo- lutional neural networks for edge intelligence”. In:Advanced Intelligent Systems 2.11 (2020), p. 2000114. (Back Cover).
  3. Yifan Qin, Rui Kuang, Xiaodi Huang, Yi Li, Jia Chen, and Xiangshui Miao. “Design of high robustness BNN inference accelerator based on binary memristors”. In: IEEE Transactions on Electron Devices 67.8 (2020), pp. 3435–3441.

Conference

  1. Yifan Qin, Zhenge Jia, Zheyu Yan, Jay Mok, Manto Yung, Yu Liu, Xuejiao Liu, Wujie Wen, Luhong Liang, Kwang-Ting Tim Cheng, X. Sharon Hu and Yiyu Shi, “A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection,” in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.

  2. Jianbo Liu, Zephan Enciso, Boyang Cheng, Likai Pei, Steven Davis, Yifan Qin, Zhenge Jia, Xiaobo Sharon Hu, Yiyu Shi and Ningyuan Cao, “A 65nm Uncertainty-quantifiable Ventricular Arrhythmia Detection Engine with 1.75μJ per Inference,” in Proc. of IEEE International Solid- State Circuits Conference (ISSCC), 2025.

  3. Yifan Qin, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi, “Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators”. In: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2024.

  4. Likai Pei*, Yifan Qin*, Zephan M. Enciso, Boyang Cheng, Jianbo Liu, Steven Davis, Zhenge Jia, Michael Niemier, Yiyu Shi, X. Sharon Hu and Ningyuan Cao. “Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks”. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024. (*Equal contribution)(acceptance rate 24%)(2024 William J. McCalla Best Paper Award Candidate)(10 out of 802 submissions)

  5. Yifan Qin, Zheyu Yan, Zixuan Pan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. “TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators”. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024.(acceptance rate 24%)

  6. Yifan Qin, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. “Negative Feedback Training: A Novel Concept to Improve Robustness of NVCiM DNN Accelerators”. In: arXiv preprint arXiv:2305.14561 (2023). (Under review)

  7. Zheyu Yan, Yifan Qin, Xiaobo Sharon Hu, and Yiyu Shi. “On the viability of using LLMs for SW/HW co-design: An example in designing CiM DNN accelerators”. In: 2023 IEEE 36th International System-on-Chip Conference (SOCC). IEEE. 2023, pp. 1–6.

  8. Zheyu Yan, Yifan Qin, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. “Improving realistic worst-case perfor- mance of NVCiM DNN accelerators through training with right-censored gaussian noise”. In: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE. 2023, pp. 1–9. (2023 William J. McCalla Best Paper Award)(2 out of 750 submissions)

Chip Demo

  • 06/2024 Life-Threatening Ventricular Arrhythmia Detection Soft/Hard-ware Co-Design Accelerator (AC-Codesign V1) ——Access center, HK

Designed and implemented a convolutional neural network system for ventricular arrhythmia detection with a 40nm LP TSMC CNN accelerator, delivering a deployable chip demo. Led the full-stack design, from UI to backend, achieving substantial reductions in inference latency and energy consumption through optimized quantization and pruning techniques, demonstrating high-performance real-time detection capabilities.

demo chip ui